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| PRELIMINARY AM29LV001B 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS s Single power supply operation -- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications -- Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors s Manufactured on 0.35 m process technology s High performance -- Full voltage range: access times as fast as 55 ns -- Regulated voltage range: access times as fast as 45 ns s Ultra low power consumption (typical values at 5 MHz) -- 200 nA Automatic Sleep mode current -- 200 nA standby mode current -- 7 mA read current -- 15 mA program/erase current s Flexible sector architecture -- One 8 Kbyte, two 4 Kbyte, and seven 16 Kbyte -- Supports full chip erase -- Sector Protection features: Hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors s Unlock Bypass Mode Program Command -- Reduces overall programming time when issuing multiple program command sequences s Top or bottom boot block configurations available s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 1,000,000 write cycle guarantee per sector s Package option -- 32-pin TSOP -- 32-pin PLCC s Compatibility with JEDEC standards -- Pinout and software compatible with singlepower supply Flash -- Superior inadvertent write protection s Data# Polling and toggle bits -- Provides a software method of detecting program or erase operation completion s Erase Suspend/Erase Resume -- Supports reading data from or programming data to a sector that is not being erased s Hardware reset pin (RESET#) -- Hardware method for resetting the device to reading array data Publication# 21557 Rev: C Amendment/0 Issue Date: April 1998 PRELIMINARY GENERAL DESCRIPTION The AM29LV001B is a 1 Mbit, 3.0 Volt-only Flash memory device organized as 131,072 bytes. The AM29LV001B has a boot sector architecture. The device is offered in 32-pin PLCC and 32-pin TSOP packages. The byte-wide (x8) data appears on DQ7- DQ0. All read, erase, and program operations are accomplished using only a single power supply. The device can also be programmed in standard EPROM programmers. The standard AM29LV001B offers access times of 45, 55, 70, and 90 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single power supply (2.7 V-3.6V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The AM29LV001B is entirely command set compatible w it h t h e J E D E C s in g le - p ow e r-s u p p ly F la s h standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal statemachine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. AM29LV001B 2 PRELIMINARY PRODUCT SELECTOR GUIDE Family Part Number Speed Options Regulated Voltage Range: VCC =3.0-3.6 V Full Voltage Range: VCC = 2.7-3.6 V Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) 45 45 25 -45R -55 55 55 30 -70 70 70 30 -90 90 90 35 AM29LV001B Note: See "AC Characteristics" for full specifications. BLOCK DIAGRAM DQ0-DQ7 VCC VSS RESET# Erase Voltage Generator Input/Output Buffers Sector Switches WE# State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch CE# OE# STB VCC Detector Timer Address Latch Y-Decoder Y-Gating X-Decoder Cell Matrix A0-A16 21557C-1 3 AM29LV001B PRELIMINARY CONNECTION DIAGRAMS A11 A9 A8 A13 A14 NC WE# VCC RESET# A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-Pin Standard TSOP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-Pin Reverse TSOP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A11 A9 A8 A13 A14 NC WE# VCC RESET# A16 A15 A12 A7 A6 A5 A4 RESET# 4 3 2 1 32 31 30 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VSS DQ3 DQ1 DQ2 DQ4 DQ5 DQ6 PLCC Am29LV001 VCC A12 A15 WE# NC A16 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 21557C-2 AM29LV001B 4 PRELIMINARY PIN CONFIGURATION A0-A16 = 17 addresses DQ0-DQ7 = 8 data inputs/outputs CE# OE# WE# RESET# VCC = Chip enable = Output enable = Write enable = Hardware reset pin, active low = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = Device ground = Pin not connected internally LOGIC SYMBOL 17 A0-A16 DQ0-DQ7 8 CE# OE# WE# RESET# VSS NC 21557C-3 5 AM29LV001B PRELIMINARY ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. AM29LV001B T -45R E C OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in (Contact an AMD representative for more information) TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) E = Extended (-55C to +125C) PACKAGE TYPE E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top Sector B = Bottom Sector DEVICE NUMBER/DESCRIPTION AM29LV001B 1 Megabit (128 K x 8-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program, and Erase Valid Combinations AM29LV001BT-45R, AM29LV001BB-45R, AM29LV001BT-55, AM29LV001BB-55, AM29LV001BT-70, AM29LV001BB-70, AM29LV001BT-90, AM29LV001BB-90, EC, EI, EE, FC, FI, FE, JC, JI, JE EC, FC, JC Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. AM29LV001B 6 PRELIMINARY DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Operation Read Write Standby Output Disable Reset Sector Protect (Note 2) Sector Unprotect (Note 2) Temporary Sector Unprotect CE# L L VCC 0.3 V L X L L X AM29LV001B Device Bus Operations OE# L H X H X H H X WE# H L X H X L L X RESET# H H VCC 0.3 V H L VID VID VID Addresses (Note 1) AIN AIN X X X Sector Address, A6 = L, A1 = H, A0 = L Sector Address, A6 = H, A1 = H, A0 = L AIN DQ0-DQ7 DOUT DIN High-Z High-Z High-Z DIN, DOUT DIN, DOUT DIN Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Don't Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A16-A0. 2. The in-system method of sector protection/unprotection is available. Sector protection/unprotection can be implemented by using programming equipment. See the "Sector Protection/Unprotection" section. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a byte, instead of four. The "Byte Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicate the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Command Definitions" section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- 7 AM29LV001B PRELIMINARY nal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7-DQ0. Standard read cycle timings and ICC read specifications apply. Refer to "Write Operation Status" for more information, and to "AC Characteristics" for timing diagrams. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.The system may use the RESET# pin to force the device into the standby mode. Refer to the "Standby Mode" section for more information. Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, RESET#: Hardware Reset Pin. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. AM29LV001B 8 PRELIMINARY Table 2. Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 A16 0 0 0 0 1 1 1 1 1 1 A15 0 0 1 1 0 0 1 1 1 1 AM29LV001B Top Boot Sector Architecture A14 0 1 0 1 0 1 0 1 1 1 A13 X X X X X X X 0 0 1 A12 X X X X X X X 0 1 X Sector Size (Kbytes) 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 4 Kbytes 4 Kbytes 8 Kbytes Address Range (in hexadecimal) 00000h-03FFFh 04000h-07FFFh 08000h-0BFFFh 0C000h-0FFFFh 10000h-13FFFh 14000h-17FFFh 18000h-1BFFFh 1C000h-1CFFFh 1D000h-1DFFFh 1E000h-1FFFFh Table 3. Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 A16 0 0 0 0 0 0 1 1 1 1 AM29LV001B Bottom Boot Sector Architecture A15 0 0 0 0 1 1 0 0 1 1 A14 0 0 0 1 0 1 0 1 0 1 A13 0 1 1 X X X X X X X A12 X 0 1 X X X X X X X Sector Size (Kbytes) 8 Kbytes 4 Kbytes 4 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes Address Range (in hexadecimal) 00000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-07FFFh 08000h-0BFFFh 0C000h-0FFFFh 10000h-13FFFh 14000h-17FFFh 18000h-1BFFFh 1C000h-1FFFFh 9 AM29LV001B PRELIMINARY Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 2). Table 4 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5. This method does not require VID. See "Command Definitions" for details on using the autoselect mode. Table 4. AM29LV001B Autoselect Codes A16 to A12 X X X A11 to A10 X X X A8 to A7 X X X A5 to A2 X X X DQ7 to DQ0 01h EDh 6Dh 01h (protected) Description Manufacturer ID: AMD Device ID: AM29LV001BT (Top Boot Block) Device ID: AM29LV001BB (Bottom Boot Block) CE# L L L OE# L L L WE# H H H A9 VID VID VID A6 L L L A1 L L L A0 L H H Sector Protection Verification L L H SA X VID X L X H L 00h (unprotected) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care. Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods. The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 1 shows the algorithms and Figure 21 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires VID on address pin A9, OE#, and RESET#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Publication number 22134 contains further details; contact an AMD representative to request a copy. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details. Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2 shows the algorithm, and Figure 20 shows the timing diagrams, for this feature. AM29LV001B 10 PRELIMINARY START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT = 1 RESET# = VID Wait 1 s Temporary Sector Unprotect Mode No First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Wait 150 s Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 No No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Temporary Sector Unprotect Mode Increment PLSCNT Reset PLSCNT = 1 Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 No No PLSCNT = 25? Yes Data = 01h? Increment PLSCNT Yes No Yes No Read from sector address with A6 = 1, A1 = 1, A0 = 0 Set up next sector address Device failed Protect another sector? No Remove VID from RESET# PLSCNT = 1000? Yes Data = 00h? Yes Device failed Write reset command Last sector verified? Yes No Sector Protect Algorithm Sector Protect complete Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete 21557C-4 Figure 1. In-System Sector Protect/Unprotect Algorithms 11 AM29LV001B PRELIMINARY against inadvertent writes (refer to Table 5 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit Perform Erase or Program Operations START RESET# = VID (Note 1) RESET# = VIH Temporary Sector Unprotect Completed (Note 2) When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. 21557C-5 Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. Figure 2. Temporary Sector Unprotect Operation Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 5 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Figure 13 shows the timing diagram. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. AM29LV001B 12 PRELIMINARY Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). See "AC Characteristics" for parameters, and to Figure 14 for the timing diagram. program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. Table 5 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set DQ5 to "1," or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". Unlock Bypass Command Sequence Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 5 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table 2 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. The unlock bypass feature allows the system to program bytes to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 5 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don't cares for both cycles. The device then returns to reading array data. Figure 3 illustrates the algorithm for the program operation. See the Erase/Program Operations table in "AC Byte Program Command Sequence The device programs one byte of data for each program operation. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The 13 AM29LV001B PRELIMINARY Characteristics" for parameters, and to Figure 15 for timing diagrams. reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to Figure 16 for timing diagrams. START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 5 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the "DQ3: Sector Erase Timer" section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the 14 Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed 21557C-6 Note: See Table 5 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 5 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware AM29LV001B PRELIMINARY sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. (Refer to "Write Operation Status" for information on these status bits.) Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to Figure 16 for timing diagrams. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are "don't-cares" when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed 21557C-7 Notes: 1. See Table 5 for erase command sequence. 2. See "DQ3: Sector Erase Timer" for more information. Figure 4. Erase Operation 15 AM29LV001B PRELIMINARY Table 5. Command Sequence (Note 1) Read (Note 5) Reset (Note 6) Manufacturer ID Autoselect (Note 7) Device ID, Top Boot Block Device ID, Bottom Boot Block Sector Protect Verify (Note 8) 4 4 3 2 2 6 6 1 1 555 555 555 XXX XXX 555 555 XXX XXX AA AA AA A0 90 AA AA B0 30 2AA 2AA 2AA PA XXX 2AA 2AA 55 55 55 PD 00 55 55 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 SA 10 30 555 555 555 90 A0 20 SA X02 PA Cycles First Addr RA XXX 555 Data RD F0 AA 2AA 55 555 90 X00 01 ED 4 555 AA 2AA 55 555 90 X01 6D 00 01 PD AM29LV001B Command Definitions Bus Cycles (Notes 2-4) Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data 1 1 4 Byte Program Unlock Bypass Unlock Bypass Program (Note 9) Unlock Bypass Reset (Note 10) Chip Erase Sector Erase Erase Suspend (Note 11) Erase Resume (Note 12) Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE# pulse. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# pulse. SA = Address of the sector to be erased or verified. Address bits A16-A12 uniquely select any sector. Notes: 1. See Table 1 for descriptions of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Address bits A16-A11 are don't care for unlock and command cycles, unless SA or PA required. 5. No unlock or command cycles required when device is in read mode. 6. The Reset command is required to return to the read mode when the device is in the autoselect mode or if DQ5 goes high. 7. The fourth cycle of the autoselect command sequence is a read cycle. 8. The data is 00h for an unprotected sector and 01h for a protected sector. The complete bus address in the fourth cycle is composed of the sector address (A16-A12), A1 = 1, and A0 = 0. 9. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 10. The Unlock Bypass Reset command is required to return to reading array data when the device is in the Unlock Bypass mode. 11. The system may read and program functions in nonerasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 12. The Erase Resume command is valid only during the Erase Suspend mode. AM29LV001B 16 PRELIMINARY WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 6 and the following subsections describe the functions of these bits. DQ7, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. START Read DQ7-DQ0 Addr = VA DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7- DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. Figure 17, Data# Polling Timings (During Embedded Algorithms), in the "AC Characteristics" section illustrates this. Table 6 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. Yes DQ7 = Data? No No DQ5 = 1? Yes Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. 21557C-8 Figure 5. Data# Polling Algorithm 17 AM29LV001B PRELIMINARY DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle (The system may use either OE# or CE# to control the read cycles). When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 6 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section "Reading Toggle Bits DQ6/DQ2" explains the algorithm. Figure 18 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 19 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section "Reading Toggle Bits DQ6/DQ2" explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 18 shows the toggle bit timing diagram. Figure 19 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6). Table 6 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm. Figure 18 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 19 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. DQ2: Toggle Bit II The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The AM29LV001B 18 PRELIMINARY DQ5: Exceeded Timing Limits START Read DQ7-DQ0 DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data. Read DQ7-DQ0 (Note 1) Toggle Bit = Toggle? Yes No DQ3: Sector Erase Timer No DQ5 = 1? Yes Read DQ7-DQ0 Twice (Notes 1, 2) After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from "0" to "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is "1", the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0", the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 6 shows the outputs for DQ3. Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to "1". See text. 21557C-9 Figure 6. Toggle Bit Algorithm 19 AM29LV001B PRELIMINARY Table 6. Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program Write Operation Status DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See "DQ5: Exceeded Timing Limits" for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. AM29LV001B 20 PRELIMINARY ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground All pins except A9, OE# and RESET# (Note 1) . . . . . . . . . . . . . . . . . . . -0.5 V to VCC+0.5 V VCC (Note 1). . . . . . . . . . . . . . . . . . . .-0.5 V to +3.6 V A9, OE#, and RESET# (Note 2) . . .-0.5 V to +12.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 21557C-10 20 ns +0.8 V -0.5 V -2.0 V 20 ns 20 ns Figure 7. Maximum Negative Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns 21557C-1 Figure 8. Maximum Positive Overshoot Waveform OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . 0C to +70C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . -40C to +85C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . -55C to +125C VCC Supply Voltages VCC for regulated voltage range. . . . . .+3.0 V to 3.6 V VCC for full voltage range . . . . . . . . . . .+2.7 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. 21 AM29LV001B PRELIMINARY DC CHARACTERISTICS CMOS Compatible Parameter ILI ILIT ILO Description Input Load Current A9 Input Load Current Output Leakage Current VCC Active Read Current (Note 1) VCC Active Write Current (Notes 2 and 4) VCC Standby Current VCC Reset Current Automatic Sleep Mode (Note 3) Input Low Voltage Input High Voltage Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 4) VCC = 3.3 V IOL = 4.0 mA, VCC = VCC min IOH = -2.0 mA, VCC = VCC min IOH = -100 A, VCC = VCC min 0.85 VCC VCC-0.4 2.3 2.5 V Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC max 5 MHz CE# = VIL, OE# = VIH 1 MHz 7 2 15 0.2 0.2 0.2 -0.5 0.7 x VCC 11.5 Min Typ Max 1.0 35 1.0 12 mA 4 30 5 5 5 0.8 VCC + 0.3 12.5 0.45 mA A A A V V V V V Unit A A A ICC1 ICC2 ICC3 ICC4 ICC5 VIL VIH VID VOL VOH1 VOH2 VLKO CE# = VIL, OE# = VIH VCC = VCC max; CE#, RESET# = VCC0.3 V VCC = VCC max; RESET# = VSS 0.3 V VIH = VCC 0.3 V; VIL = VSS 0.3 V Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Erase or Embedded Program is in progress. 3. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 4. Not 100% tested. AM29LV001B 22 PRELIMINARY DC CHARACTERISTICS (Continued) Zero Power Flash 20 Supply Current in mA 15 10 5 0 0 500 1000 1500 2000 Time in ns Note: Addresses are switching at 1 MHz 21557C-12 2500 3000 3500 4000 Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 10 8 Supply Current in mA 3.6 V 6 2.7 V 4 2 0 1 2 3 Frequency in MHz Note: T = 25 C 21557C-13 4 5 Figure 10. Typical ICC1 vs. Frequency 23 AM29LV001B PRELIMINARY TEST CONDITIONS Table 7. 3.3 V Test Condition Device Under Test CL 6.2 k Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 5 0.0-3.0 1.5 1.5 ns V V V 2.7 k Output Load Output Load Capacitance, CL (including jig capacitance) 30 -45R, -55 -70, -90 1 TTL gate 100 pF Unit Test Specifications Note: Diodes are IN3064 or equivalent 21557C-14 Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) 21557C-15 OUTPUTS 3.0 V 0.0 V Input 1.5 V Measurement Level 1.5 V Output 21557C-16 Figure 12. Input Waveforms and Measurement Levels AM29LV001B 24 PRELIMINARY AC CHARACTERISTICS Read Operations Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ Std. tRC tACC tCE tOE tDF tDF Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Read tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling CE# = VIL OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Min Min Min -45R 45 45 45 25 10 10 Speed Option -55 55 55 55 30 15 15 0 10 0 -70 70 70 70 30 25 25 -90 90 90 90 35 30 30 Unit ns ns ns ns ns ns ns ns ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Notes: 1. Not 100% tested. 2. See Figure 11 and Table 7 for test specifications. tRC Addresses CE# tOE tOEH WE# HIGH Z Outputs RESET# n/a Am29F002NB Addresses Stable tACC tDF OE# tCE tOH HIGH Z Output Valid 21557C-17 Figure 13. Read Operations Timings 25 AM29LV001B PRELIMINARY AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std. tREADY tREADY tRP tRH tRPD Description RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) RESET# Pulse Width RESET# High Time Before Read (See Note) RESET# Low to Standby Mode Test Setup Max Max Min Min Min All Speed Options 20 500 500 50 20 Unit s ns ns ns s Note: Not 100% tested. CE#, OE# tRH RESET# n/a Am29F002NB tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms RESET# n/a Am29F002NB tRP 21557C-18 Figure 14. RESET# Timings AM29LV001B 26 PRELIMINARY AC CHARACTERISTICS Erase/Program Operations Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX Std. tWC tAS tAH tDS tDH tOES tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tGHWL tCS tCH tWP tWPH Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (Note 1) Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Min Min Min Min Min Min Min Min Min Min Min Typ Typ Min 25 30 30 9 0.7 50 35 20 45 20 0 0 0 0 0 35 35 -45R 45 -55 55 0 45 35 45 45 -70 70 -90 90 Unit ns ns ns ns ns ns ns ns ns ns ns s sec s tWHWH1 Programming Operation (Note 2) tWHWH2 Sector Erase Operation (Note 2) tVCS VCC Setup Time (Note 1) Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" Section for more information. 27 AM29LV001B PRELIMINARY AC CHARACTERISTICS Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# tGHWL OE# tWP WE# tCS tDS Data tDH PD Status DOUT tWPH tWHWH1 PA PA Read Status Data (last two cycles) tCH A0h VCC tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 21557C-19 Figure 15. Program Operation Timings AM29LV001B 28 PRELIMINARY AC CHARACTERISTICS Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA 555h for chip erase Read Status Data VA tAH VA CE# tGHWL OE# tWP WE# tCS tDS tDH Data tVCS VCC 55h 30h 10 for Chip Erase In Progress Complete tCH tWPH tWHWH2 Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status"). 21557C-20 Figure 16. Chip/Sector Erase Operation Timings 29 AM29LV001B PRELIMINARY AC CHARACTERISTICS tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7 High Z VA VA tOE tDF Complement Complement True Valid Data High Z DQ0-DQ6 Status Data Status Data True Valid Data Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 21557C-21 Figure 17. Data# Polling Timings (During Embedded Algorithms) tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ6/DQ2 High Z VA VA VA tOE tDF Valid Status (first read) Valid Status (second read) Valid Status (stops toggling) Valid Data Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 21557C-22 Figure 18. Toggle Bit Timings (During Embedded Algorithms) AM29LV001B 30 PRELIMINARY AC CHARACTERISTICS Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note: The system can use OE# or CE# to toggle DQ2/DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. 21557C-23 Figure 19. DQ2 vs. DQ6 Temporary Sector Unprotect Parameter JEDEC Std. tVIDR tRSP Description VID Rise and Fall Time RESET# Setup Time for Temporary Sector Unprotect Min Min All Speed Options 500 4 Unit ns s Note: Not 100% tested. 12 V RESET# 0 or 3 V tVIDR Program or Erase Command Sequence CE# tVIDR 0 or 3 V WE# tRSP RY/BY# 21557C-24 Figure 20. Temporary Sector Unprotect Timing Diagram 31 AM29LV001B PRELIMINARY AC CHARACTERISTICS VID VIH RESET# SA, A6, A1, A0 Valid* Sector Protect/Unprotect Valid* Verify 40h Sector Protect: 100 s Sector Unprotect: 10 ms Valid* Data 1 s CE# 60h 60h Status WE# OE# Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. 21557C-25 Figure 21. In-System Sector Protect/Unprotect Timing Diagram AM29LV001B 32 PRELIMINARY AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter JEDEC tAVAV tAVEL tELAX tDVEH tEHDX Std. tWC tAS tAH tDS tDH tOES tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (Note 1) Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation (Notes 1, 2) Sector Erase Operation (Notes 1, 2) Min Min Min Min Min Min Min Min Min Min Min Typ Typ 25 30 30 9 0.7 35 20 45 20 0 0 0 0 0 35 35 -45 45 -55 55 0 45 35 45 45 -70 70 -90 90 Unit ns ns ns ns ns ns ns ns ns ns ns s sec Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" Section for more information. 33 AM29LV001B PRELIMINARY AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling PA Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tAS tAH tWHWH1 or 2 DQ7# DOUT RESET# Notes: 1. Figure indicates the last two bus cycles of the program or erase command sequence. 2. PA program address, SA = Sector Address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 21557C-26 Figure 22. Alternate CE# Controlled Write Operation Timings AM29LV001B 34 PRELIMINARY ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time (Note 3) Typ (Note 1) 0.7 7 9 1.1 300 3.3 Max (Note 2) 15 Unit s s s s Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 2.7 V (3.0 V for -45R), 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min -1.0 V -1.0 V -100 mA Max 13.0 V VCC + 1.0 V +100 mA Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP PIN CAPACITANCE Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz. PLCC PIN CAPACITANCE Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VPP = 0 Typ 4 8 8 Max 6 12 12 Unit pF pF pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz. 35 AM29LV001B PRELIMINARY PHYSICAL DIMENSIONS PL 032 32-Pin Plastic Leaded Chip Carrier (measured in inches) .447 .453 .485 .495 .009 .015 .125 .140 .080 .095 SEATING PLANE .400 REF. .013 .021 .490 .530 .042 .056 .585 .595 .547 .553 Pin 1 I.D. .026 .032 TOP VIEW .050 REF. SIDE VIEW 16-038FPO-5 PL 032 DA79 6-28-94 ae AM29LV001B 36 PRELIMINARY PHYSICAL DIMENSIONS* TS 032 32-Pin Standard Thin Small Outline Package (measured in millimeters) 0.95 1.05 Pin 1 I.D. 1 7.90 8.10 0.50 BSC 18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21 0.05 0.15 1.20 MAX 0 5 0.50 0.70 16-038-TSOP-2 TS 032 DA95 3-25-97 lv * For reference only. BSC is an ANSI standard for Basic Space Centering 37 AM29LV001B PRELIMINARY PHYSICAL DIMENSIONS* TSR032 32-Pin Reverse Thin Small Outline Package (measured in millimeters) 0.95 1.05 Pin 1 I.D. 1 7.90 8.10 0.50 BSC 18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21 0.05 0.15 1.20 MAX 0.25MM (0.0098") BSC 0 5 0.50 0.70 16-038-TSOP-2 TSR032 DA95 4-4-95 ae * For reference only. BSC is an ANSI standard for Basic Space Centering REVISION SUMMARY FOR AM29LV001B Revision B Split the AM29LV001B/Am29LV010B data sheet, with the elimination of all references to Am29LV010B. Distinctive Characteristics Changed process technology to 0.33 m. Temporary Sector Unprotect Entered timing specifications for tVIDR and tRSP. Erase and Programming Performance Changed endurance in Note 2 to 1 million cycles; added worst case voltage for -45R speed option. Revision C Global Deleted 120 ns speed option; added 90 ns speed option. Trademarks Copyright (c) 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. AM29LV001B 38 |
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